Though IC manufacturing technology is mature, random defects are still a main factor causing yield loss. The accurate analysis of critical areas, where the center of a certain-size defect falls into to cause a functional failure in ICs, is critical for designers to gain a deep understanding of potential issues within their designs.

Virtual Yield is an automated tool used to predict and analyze product yield based on yield models and chip layouts. By providing accurate prediction data for product yield and report that compares yield influencing factors, Virtual Yield helps designers prioritize and gain insights into the factors and makes the IC product more manufacturing friendly.