Semitronix has spent 10+ years to innovate test chip design methodology and developed a series of addressable test chips, which improve the density of test chips by 5X~20X, while achieving the best measurement accuracy in the field. These series of test chips have been extensively verified and adopted by many leading fabs worldwide on the process development and yield improvement of multiple nodes, and help to achieve the objectives of short development cycle and high quality production.

Due to various requirements of test key types, semitronix provides multiple addressable IP options. Current addressable IP family is listed as below:

• Addressable transistor array IP
• Addressable yield array IP
• Addressable ring oscillator IP
• Addressable CBCM/QVCM IP

• PCell based DOE layout auto creation
• Support existing layout import 
• Auto placing/routing
• Auto floorplanning
• Auto connection check
• Auto DRC verification
• Auto LVS verification
• Auto design documentation
• Auto testing program generation