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DFT Design Service

Enhances the testability of chips by inserting test circuits into the chip design

Introduction

DFT (Design for Test) technology is widely recognized in the industry as a standard practice that involves inserting dedicated test circuits into the chip design to improve the testability of chips. The industry faces the challenges to reduce testing costs while ensuring that the test circuitry occupies a small area on the chip design to achieve higher fault coverage.

Semitronix and Yichip have jointly introduced the DFT automation and yield diagnostics service. The service is used by top domestic design houses to cover the following scenarios: MCU, ADAS, GPU, CPU, AI, 5G, and video processing. Users can address the challenges of diagnosing and testing SoC and large-scale chips, performing functional safety testing for automotive devices, and enhancing yield to improve product quality and reduce costs.

Architecture Definition

Test Mode Definition
IO plan、Test Plan、Burn-In plan
MBIST、Repair、SCAN、Logic BIST、In-System-Test、BSCAN Structure Definition
3rd-party IP Test Interface Definition

Automotive DFT

In-System-Test
IST Controller and LBIST Controller Insertion
DMA Mode IST Integration to Support Power Self-test
CPU Interface IST Integration to Support Periodic Self-test
IST +MBIST+LBIST Verification
Low DPPM solution
Automotive Level ATPG
User Defined MBIST Algorithm
High Coverage Implementation( Scan Structure + Testpoint)

DFT Flow Development

DFT Insert：IST Controller、MBIST、Repair、BSCAN、IJTAG Network、OCC、Compress Structure、Logic BIST Controller Insertion
SCAN Insertion and Hierarchical ATPG
Pre-sim+Post-sim Simulation Environment
Formal Check、 DFT SDC Integration
Cell Aware ATPG、Diagnosis and Yield Improvement Flow

DFT Project Implementation

RTL Insertion
Block level and Top level Insertion for MBIST,Compress, OCC, BSCAN, LBIST, IST, IJTAG Network
Scan Insertion
SCAN Chain、Wrapper Cell Insertion and EDT Connection
ATPG
Graybox Generation and DC/AC ATPG
Simulation
MBIST、BSCAN、IJTAG Network、Chain/AC/DC Simulation
SDC
MBIST&AC Capture、Scan Shift、DC Capture SDC Generation，Flattern SDC Generation
Formal Check
Pre-DFT vs Post-DFT

Diagnosis and Yield Improvement

ATPG Diagnosis
Diagnosis Environment Setup
Chain Diagnosis Flow Build up
Layout Aware Scan Diagnosis
Transition Diagnosis
Cell Aware Diagnosis
Yield Analysis Flow Setup
MBIST Diagnosis
Build Lab MBIST Diagnosis
Build Mass Products MBIST Diagnosis